/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "defines.v"
`timescale 1ns/1ps

module imm_src(
	input	wire[`InstDataBus]		inst_i,
	input	wire[2:0]				mux_imm_src_i,

	output	wire[`RegDataBus]		imm_data_o
	);

	wire[`RegDataBus] imm_src_case_1 = {{52{inst_i[31]}}, inst_i[31:20]};
	wire[`RegDataBus] imm_src_case_2 = {{52{inst_i[31]}}, inst_i[31:25],
		inst_i[11:7]};
	wire[`RegDataBus] imm_src_case_3 = {{52{inst_i[31]}}, inst_i[7],
		inst_i[30:25], inst_i[11:8], 1'b0};
	wire[`RegDataBus] imm_src_case_4 = {{44{inst_i[31]}}, inst_i[19:12],
		inst_i[20], inst_i[30:21], 1'b0};
	wire[`RegDataBus] imm_src_case_5 = {{32{inst_i[31]}}, inst_i[31:12], 12'h0};
	wire[`RegDataBus] imm_src_case_6 = {58'h0, inst_i[25:20]};

	assign imm_data_o = ({`XLEN{mux_imm_src_i == 3'b000}} & imm_src_case_1)
		| ({`XLEN{mux_imm_src_i == 3'b001}} & imm_src_case_2)
		| ({`XLEN{mux_imm_src_i == 3'b010}} & imm_src_case_3)
		| ({`XLEN{mux_imm_src_i == 3'b011}} & imm_src_case_4)
		| ({`XLEN{mux_imm_src_i == 3'b100}} & imm_src_case_5)
		| ({`XLEN{mux_imm_src_i == 3'b101}} & imm_src_case_6);

endmodule
